1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device and a test method thereof, and particularly to a fault detection technique for a semiconductor IC device.
2. Description of the Related Art
In general, test patterns for normal (ordinary) operations are manually generated with the aim of function verification, and are also used for shipping tests in mass production of LSI (Large Scale Integrated circuit) products, such as microcomputers. In order to improve the fault coverage (detection rate of faults), this method may proceed with the following procedures. First, a fault simulation is performed on a target LSI, using test patterns, and a non-detected fault list obtained thereby is checked. Then, test patterns, which seem to allow non-detected faults to be detected, are added, and a fault simulation is performed again to confirm effects of the test patterns.
This method is the lowest in area cost, because there is no need to add any test circuit. In addition, this method easily achieves a relatively high fault coverage (about 85% to 92%). However, with this method, it is very difficult, using only test patterns from the outside, to completely detect non-detected faults of logics deep in an LSI or non-detected faults that are hardly detected by setting a test environment of an LSI. Consequently, it is necessary to take great effort to achieve a high fault coverage of, e.g., 95% or more, which is required for LSI products in recent years. This method also entails another problem in that it cannot necessarily guarantee to reach a target value.
On the other hand, a design for testability (test facilitating design) on the basis of full scan design, which is used for large-scale system LSI products, easily provides test patterns achieving a fault coverage of 95% or more by an ATPG (Automatic Test Pattern Generation) tool. However, this design method requires almost all the internal flip-flops and latches to be scannable (a circuit structure that can be scan-operable), which may give rise to an increase in area of from 5% to 20%. For this reason, this design method is not necessarily a satisfactory solution for microcomputer products or the like, which are manufactured in a very high volume over a long period of time and suffer severe cost competition.
FIG. 17A is a block diagram schematically showing the internal structure of a conventional semiconductor integrated circuit device (LSI). As shown in FIG. 17A, a combinational logic (random logic) 200, and flip-flops 210-1 to 210-4 used as memory elements of an LSI 100 are arranged in the LSI 100.
FIG. 17B is a block diagram schematically showing the internal structure of a conventional semiconductor IC device, formed by modifying the structure shown in FIG. 17A with a basic scan design method, in which a clock for scanning is common to the system clock. An explanation will be given of the basic scan design method with reference to FIG. 17B.
As shown in FIG. 17B, multiplexers 220-1 to 220-4 to be controlled by a test mode signal TEST are disposed immediately before the inputs D of the flip-flops 210-1 to 210-4, respectively. The multiplexer 220-1 at the first stage receives as inputs a test pattern inputted from a scan-in terminal SI, and an output of the combinational logic 200. These inputs are subjected to a selection operation by the multiplexer 220-1 on the basis of the TEST signal, so that the selected one is inputted into the flip-flop 210-1. The multiplexer 220-2 at the next stage receives as inputs the output Q of the flip-flop 210-1 and an output of the combinational logic 200. These inputs are subjected to a selection operation by the multiplexer 220-2 on the basis of the TEST signal, so that the selected one is inputted into the flip-flop 210-2. A similar arrangement is formed for each of the flip-flops 210-3 and 210-4 at the following stages. The output of the flip-flop 210-4 at the final stage comes to a scan-out terminal SO.
In the device described above, when TEST=0, a normal (ordinary) operation is performed. Specifically, outputs of the combinational logic 200 in the ordinary operation are respectively stored in the flip-flops 210-1 to 210-4 in synchronism with a clock. When TEST=1, a scanning operation is performed. Specifically, all the flip-flops 210-1 to 210-4 operate as a shift register, using the scan-in terminal SI as the input, and the scan-out terminal SO as the output. Accordingly, arbitral test data can be serially inputted from the outside of the LSI 100 into the flip-flops 210-1 to 210-4. Furthermore, these contents can be read out of the LSI 100 (scan-operable).
The scanning test is performed by repeating the following two steps.
(1) When TEST=1, setting of the necessary test data, and readout of a test result are serially performed.
(2) When TEST=0, a test result in a normal operation is stored in the respective flip-flops.
As described above, with this scan design method, flip-flops and latches in an LSI can be treated imaginarily equivalently to input and output terminals of the LSI. Accordingly, a test pattern generating algorithm on a combinational circuit can be applied to this test pattern generation, thereby, at present, allowing a high fault coverage to be relatively easily obtained, using a commercially available ATPG tool. However, as mentioned above, the scan design method requires almost all the internal flip-flops and latches to be scannable in order to reliably obtain a high fault coverage. This brings about a problem of a remarkable increase in area. Furthermore, depending on the method of implementation, such as adding multiplexers or the like, as shown in FIG. 17, the performance (e.g., operation frequency) in the normal operations may be lowered.
On the other hand, there is a method of adding observation points to improve a fault coverage on a test target LSI. The simplest method is to lead a node to be observed to an output terminal of an LSI, and to directly observe it when a test is executed. However, this method cannot be a practical solution, because the number of terminals increases with an increase in the number of observation points. As a countermeasure against this problem, there is a proposal to input the data from observation points into an exclusive OR (XOR) gate, and to observe only its output. In this case, however, it is difficult to analyze a generated fault at one of the observantion points. Furthermore, where an even number of the observation points output at the same time a logical value, which is not correct due to a fault in an LSI, the output of an XOR gate becomes the same as the normal state, thereby preventing the fault from being detected (fault masking). Accordingly, not allowing a number of observation points to be put together, this method cannot essentially solve the problem described above in which the number of terminals of an LSI increases with an increase in the number of observation points.
In light of the problems described above, where an LSI includes a number of observation points therein, a parallel-input signature-compression (compressing pieces of applied test data to generate own signatures corresponding to the pieces of test data) register is used in general as a conventional method to prevent the number of terminals of the LSI from increasing. This method is utilized in the manner of, e.g., arranging an observation register in a microprocessor or the like. FIG. 18 is a circuit diagram showing a conventional observation circuit in a semiconductor IC device for this method. FIG. 18 shows a basic structure including a part other than signature-compression (four bit width). This is almost the same as that of a circuit known as BILBO (Built-In Logic Block Observer).
As shown in FIG. 18, this device includes four flip-flops 210-5 to 210-8 operated by a clock CLK. The output of the flip-flop 210-7 at the third stage and the output of the flip-flop 210-8 at the fourth stage are subjected to an exclusive OR operation by an XOR gate 230-1. This operation result and a test pattern from a scan-in terminal SI are subjected to a selection operation by a multiplexer 240 on the basis of a signal A. The scan-in terminal SI is an input terminal of an LSI 100, for example.
Where respective signals observed at observation points are named signals D[0] to D[3], the respective signals D[0] to D[3] and the signal A are subjected to an AND operation by AND gates 250-1 to 250-4. A signal selected by the multiplexer 240 and the signal B are subjected to an AND operation by an AND gate 250-5. This operation result and the output of the AND gate 250-1 are subjected to an exclusive OR operation by an XOR gate 230-2. This operation result comes to the input D of the flip-flop 210-5. The output Q of the flip-flop 210-5 and the signal B are subjected to an AND operation by an AND gate 250-6. This operation result and the output of the AND gate 250-2 are subjected to an exclusive OR operation by an XOR gate 230-3. This operation result comes to the input D of the flip-flop 210-6.
Then, similarly, the respective outputs Q of the flip-flops 210-6 and 210-7 and the signal B are subjected to an AND operation by AND gates 250-7 and 250-8. These operation results and the outputs of AND gates 250-3 and 250-4 are subjected to an exclusive OR operation by XOR gates 230-4 and 230-5, respectively. These outputs come to the inputs D of the flip-flops 210-7 and 210-8 at the following stages, respectively. The output Q of the flip-flop 210-8 is outputted from a scan-out terminal SO through a buffer 260. The scan-out terminal SO is an output terminal of the LSI 100, for example. In general, the outputs Q[0] to Q[3] of the flip-flops 210-5 to 210-8 come to inputs of another circuit block in the LSI 100.
Operations of the circuit are controlled by the signals A and B, as shown in Table 1.
TABLE 1ABOPERATION00RESET (“0” INTO ALL FLIP-FLOPS)01SERIAL10TEST DATA CAPTURE (NORMAL)11SIGNATURE-COMPRESSION
An explanation will be given of the operations, focusing on one bit (the flip-flop 210-6) shown in FIG. 18.
When A=0 and B=0, both the outputs of the AND gates 250-2 and 250-6 become “0”, and the output of the XOR gate 230-3 also becomes “0”. Accordingly, “0” is inputted into all the flip-flops including the flip-flop 210-6, thereby performing a reset operation.
When A=0 and B=1, the multiplexer 240 selects data inputted from the scan-in terminal SI. The output of the XOR gate 230-3 becomes the same as the output of the AND gate 250-6 (, which is equivalent to the output of the flip-flop 210-5). As a whole, the four flip-flops 210-5 to 210-8 are in a state of being connected in series, and perform a serial operation in synchronism with a clock.
When A=1 and B=0, a value the same as the D[1] is stored in the flip-flop 210-6. As a whole, they perform an operation of capturing the outputs of the observation points.
When A=1 and B=1, an exclusive OR between the D[1] and the output Q of the flip-flop 210-5 (one stage prior to the flip-flop 210-6) is stored in the flip-flop 210-6. At the same time, an exclusive OR between the output of the XOR gate 230-1 and the D[0] is stored in the flip-flop 210-5 at bit “0”. Consequently, as a whole, they become a signature-compression register to perform a signature-compression operation. In this operation, on the basis of data in the flip-flop and the outputs newly applied from observation points, pseudo-random data is generated in the flip-flops. When the test is completed, data (a signature) peculiar to the sequence of the output data from the observation points is stored in the flip-flops as a test result.
The steps of the test are as follows. Specifically, A=0 and B=0 are first set to cause the contents of the flip-flop to be “0”, before the first data to be observed is outputted. Then, A=1 and B=1 are set to perform signature-compression on all the effective output from the observation points. After the test is completed, A=0 and B=1 are set to cause the flip-flops, which are inside the signature-compression register, to perform a serial operation. Then, a test result is serially read out of the LSI, and is compared with an expected value for the normal circuit to judge whether there is a fault or not. There are various methods logically realized as a method of performing this readout, including the relationship relative to test mode signals.
When A=1 and B=0, the outputs from the observation points can be stored in the flip-flops, just as they are. Accordingly, fault diagnosis can be performed on the observation point in the LSI by the following method. Specifically, in arbitral one cycle of the normal operations, A=1 and B=0 are first set to store data from the observation points in a normal operation, and then A=0 and B=1 are set to serially output the stored data out of the LSI.
However, the conventional method of inserting observation points described above has been no more than a unsatisfactory method using an observation circuit to improve observation, thereby expecting an improvement in the fault coverage to some extent. In this method, observation points are arranged without clearly recognizing faults to be detected. Consequently, it is not satisfactory in terms of optimizing or minimizing circuits added for observation. Furthermore, this method pays no attention to the technique of determining a control system, sufficiently considering characteristics of test patterns applied to a test target LSI. Consequently, it may not improve the fault coverage up to the expectation, even though an observation circuit is added.
As described above, the conventional method of inserting observation points for fault detection and diagnosis on an LSI is performed without clearly recognizing faults to be detected. As a result, the area efficiency of the LSI is deteriorated, although the fault coverage is improved to some extent. Furthermore, the conventional method pays no attention to a technique of determining a control system sufficiently considering characteristics of test patterns. As a result, the effect of improving the fault coverage is not sufficient.